1. Field of the Invention
The present invention relates to a memory hierarchically constructed of memory cells which are combined to form memory groups, and in which a column circuit and a row circuit for selecting, reading and writing are assigned to each memory cell in the memory group so that a memory is divided into more than two hierarchy levels.
2. Description of the Prior Art
As reported in the publication ISSCC Digest of Technical Papers, 1988, Session 13: "Static RAMs", fast static memories constructed in complementary metal-oxide-semiconductor (CMOS) technology are usually realized with four or six transistor cells in at most two hierarchy levels. A higher speed is usually achieved with an improvement of the technology in view of the structure fineness, of the multi-layer wiring and specific process options such as "buried contact" or high-impedance polysilicon.
Within a given process, however, speed advantages can also be achieved with circuit-oriented measures. To this end, it has already been proposed to shorten the access time by the introduction of a plurality of hierarchy levels since the delay times on long word and data lines are avoided. However, a dynamic one-transistor memory cell is considered for this purpose in the publication by C. Mead and L. Conway, "Introduction to VLSI-Systems", Second Edition, Addison-Wesley, 1980, Chapter 8.5. FIG. 8.31 of this publication shows a memory divided into two hierarchy levels that, however, does not contain any more detailed particulars regarding the construction of periphery circuits, such as decoders and read amplifiers. The structure of the first hierarchy level for a 16 cell block is shown in FIG. 8.32 of the publication. The speed advantage made possible by the hierarchal structure is acquired at the expense of an increased speed due to the multiplication of the drive and read circuits, particularly on the first hierarchy level.